Application Specific Integrated Circuits (ASICs) are commonly used to perform a variety of functions in electronically controlled devices and systems. In operation, ASICs should be resetable to a defined state (e.g., initial state, and the like).
Conventionally, resetting an ASIC to the defined state is accomplished by generating a reset signal and applying that signal to reset pins of the storage cells of the ASIC, such as D-type flip-flops, and the like.
However, in large ASICs, as well as the ASICs having multiple clock domains, loading conditions and propagation delays associated with the reset signal may result in asynchronous resetting of the storage cells, thus causing setup/hold time violations and failures within the ASIC.